1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device with an internal wiring layer and a method of fabricating the same.
2. Description of the Related Art
Conventional examples of a semiconductor device with a wiring layer in a semiconductor substrate are a dynamic RAM cell disclosed in "A 4.2 .mu.m.sup.2 Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate-Wiring" T. Kaga et al., International Electron Devices Meeting Technical Digest, 1987, pp. 332 to 335 and a dynamic RAM cell disclosed in "Semiconductor Memory Having Trench Capacitor Formed With Sheath Electrode" U.S. Pat. No. 4,918,502 to T. Kaga et al.
Each DRAM cell disclosed in the above literature has an N-type diffusion layer formed by diffusion into a P-type substrate from the bottom of each trench formed in the P-type substrate. These N-type diffusion layers are electrically connected with each other by contacting each other to thereby constitute a wiring layer inside the substrate. This wiring layer in the above DRAM cell functions as a wire for applying a potential to the plate electrode of a capacitor. In this DRAM cell, however, the wiring layer is formed inside the substrate. Therefore, applying a potential to this wiring layer requires a specific design: one of trenches is caused to serve as an exclusive terminal for the potential supply. For this reason, in the above cell, one trench is caused to serve as a terminal (to be referred to as a "terminal trench" hereinafter) as follows. An oxide film is formed on the side walls of a trench in order to constitute a so-called "sheath capacitor." In the terminal trench, this oxide film is removed by photolithography and an N-type diffusion layer is formed on the entire surfaces of the trench. This N-type diffusion layer is formed in contact with N-type diffusion layers formed by diffusion from the bottoms of the other trenches to together serve as a wiring layer. A potential is supplied to these N-type diffusion layers serving as a wiring layer from the diffusion layer formed on the entire surfaces of the terminal trench. The device of this type is described in, e.g., U.S. Pat. No. 4,918,502 with reference to FIGS. 10D to 10N.
In a semiconductor device having a wiring layer inside a semiconductor substrate, it is not easy to apply a potential to the wiring layer. To supply a potential, therefore, a special design such as formation of a terminal trench 1 as shown in FIGS. 1 and 2 is used. This requires an additional photolithography step or the like, and the result is complexity in the whole fabrication process. Especially in formation of the terminal trench 1, a resist 5 must be removed from the terminal trench 1 in order to selectively remove an oxide film 6 on the side surfaces of the trench 1. In this case, if misalignment of patterns occurs as indicated by a resist 5' in FIG. 1, a disconnected portion 8a is formed between an N-type diffusion layer 8 around the terminal trench 1 and an N-type diffusion layer 7 at the bottom of a trench 2, preventing these diffusion layers from making contact with each other. In addition, it is highly probable that the resist 5 is not completely removed but left behind in the terminal trench 1. If the resist 5 remains in the terminal trench 1, the oxide film 6 is not completely removed, and an unremoved portion 6a remains on the wall surface of the terminal trench 1, as shown in FIG. 2. This residual oxide film 6a acts as a diffusion mask to cause, e.g., a diffusion error 8b. The diffusion error 8b introduces problems such as a disconnection in the N-type diffusion layer 8 or an increase in contact resistance between the wiring layer and the terminal. In addition, if the resist remains in the terminal trench, harmful impurities (such as heavy metals) contained in the resist may diffuse into the device to contaminate it. Note that reference numeral 3 denotes an element isolating SiO.sub.2 film; 4, an Si.sub.3 N.sub.4 film; and 10, a P-type semiconductor substrate.